The present invention generally relates to secondary cell searching within 3rd generation (3G) wireless networks.
Universal Mobile Telecommunications System (UMTS) is a standard for 3G wireless networks, as defined by the International Telecommunications Union. UMTS defines a communication scheme composed of slots (2560 chips/slot), with 15 slots forming a frame (38,400 chips per frame). As is known, “chip” or “chip rate” refers to the rate of the spreading code within a Code Division Multiple Access (CDMA) communication system. Each slot specifies, among other data, synchronization information used to synchronize communications between nodes of a UMTS compliant network.
An important procedure performed by a receiver within a UMTS network, for example one disposed within a mobile terminal, is the cell search operation. A cell search operation typically is performed after the receiver is powered on to determine synchronization information pertaining to the cell in which the receiver is located. The cell search operation generally accomplishes three things: slot synchronization, frame synchronization, and scrambling code determination.
In performing the cell search operation, the receiver accesses a Synchronization Channel (SCH) and a Common Pilot Channel (CPICH) of the transmitted signal. The SCH is a composite channel formed from a Primary SCH and a Secondary SCH. Within each slot, the Primary SCH specifies a Primary Synchronization Code (PSC). However, the Primary SCH only contains data during the first 256 chips of each 2560 chip slot.
The receiver uses the Primary SCH to acquire slot synchronization with a cell. Typically this is performed using a single matched filter, or other similar device. The filter is matched to the PSC which is common to all cells. The slot timing of a cell can be obtained by detecting peaks in the matched filter output.
The receiver performs frame synchronization using the Secondary SCH. The Secondary SCH specifies, within each slot, a Secondary Synchronization Code (SSC). Unlike the PSC, the SSC can be one of 16 different codes and each slot contains one SSC. The SSC used varies from slot to slot to form a sequence that has a period of one frame, or 15 slots. There are 64 possible SSC sequences and each sequence corresponds to one of 64 possible scrambling code groups. By observing a full frame of data, the receiver can determine which of the 64 SSC sequences is being transmitted. Since the SSC sequence repeats with a period equal to one frame, the sequence can be used to achieve frame synchronization at the receiver because frame boundaries can be identified. The SSC sequence that is transmitted further indicates which scrambling code group is used in the current cell.
Each scrambling code group includes 8 possible scrambling codes. To determine the actual scrambling code, the received CPICH signal can be correlated with each of the 8 possible scrambling codes in the identified scrambling code group until the correct scrambling code is determined. After the actual scrambling code has been identified, the Primary Common Control Channel (CCPCH) can be detected so that system and cell specific Broadcast Channel (BCH) information can be read.
A typical approach to Secondary SCH acquisition is to store, for each slot, the index of the strongest of the 16 SSC correlations. To find the SSC sequence with the highest number of matches, the resulting 15 indices are compared to reference sequences for all 64 possible scrambling code groups. From this comparison, the transmitted scrambling code group and the frame offset can be determined.
The processor used for Primary SCH acquisition typically is a single hardware device that is implemented with sub-chip accuracy. This higher accuracy allows the receiver to start the Secondary SCH correlation with improved accuracy. Because Secondary SCH processing involves performing 16 parallel correlations, one correlation for each of the 16 possible transmitted SSC codes, the Secondary SCH processors frequently are configured to use a single sample per chip to ease hardware requirements.
In an ideal environment, use of one sample per chip for Secondary Synchronization would not be problematic as the primary SCH processor would ideally synchronize to within a ¼ chip of the actual start of the slot. Accordingly, the Secondary SCH processor would work successfully despite using a single sample per chip. In practice, however, harsh channel environments can result in offsets of a ¼ of a chip or more during Primary Synchronization due to noise and other channel effects or distortions. If such synchronization offsets occur, performing Secondary Synchronization with only one sample per chip can result in a degraded correlation peak or, possibly, a completely erroneous correlation.
It would be desirable to perform Secondary SCH correlations with sub-chip accuracy while avoiding the significant increase in hardware that would result from implementing a typical sub-chip accurate Secondary SCH processor.